Kioxia Develops Core Technology that Will Allow the Practical Implementation of High-density, Low-power 3D DRAM>

(BUSINESS WIRE)--Kioxia Corporation, a world leader in memory solutions, today announced the development of highly stackable oxide-semiconductor channel transistors that will enable the practical implementation of high-density, low-power 3D DRAM. This technology was presented at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, USA, on December 10, and has the potential to reduce power consumption across a wide range of applications, including AI servers and IoT components. In the era of AI, there is growing demand for DRAM with larger capacity and lower power consumption that can process large amounts of data. Traditional DRAM technology is reaching the physical limits of memory cell size scaling, prompting research into the 3D stacking of memory cells to provide additional capacity. The use of single-crystal silicon as the channel material for transistors in stacked memory cells, as is the case with conventional DRAM, drives up manufacturing costs, and the power required to refresh the memory cells increases proportionally to the memory capacity. At last year’s IEDM, we announced the development of Oxide-Semiconductor Channel Transistor DRA...(BUSINESS WIRE)--Kioxia Corporation, a world leader in memory solutions, today announced the development of highly stackable oxide-semiconductor channel transistors that will enable the practical implementation of high-density, low-power 3D DRAM. This technology was presented at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, USA, on December 10, and has the potential to reduce power consumption across a wide range of applications, including AI servers and IoT components. In the era of AI, there is growing demand for DRAM with larger capacity and lower power consumption that can process large amounts of data. Traditional DRAM technology is reaching the physical limits of memory cell size scaling, prompting research into the 3D stacking of memory cells to provide additional capacity. The use of single-crystal silicon as the channel material for transistors in stacked memory cells, as is the case with conventional DRAM, drives up manufacturing costs, and the power required to refresh the memory cells increases proportionally to the memory capacity. At last year’s IEDM, we announced the development of Oxide-Semiconductor Channel Transistor DRA...{}